`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Merlionfire
// 
// Create Date:    06:53:21 02/01/2015 
// Design Name: 
// Module Name:    keyboard_decoder 
// Project Name:   ping-pong-fpga  
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module keyboard(
   // Clock and reset    
   input wire  clk,
   input wire       rst,
   // PS/2 interface 
   input wire       ps2_clk,
   input wire       ps2_data,
   input wire       ps2_rx_en, 
   // Ping-pong interface
   output reg       key_up_tick,   
   output reg       key_down_tick 
 );


   parameter KEY_W  =   8'h1D ; 
   parameter KEY_S  =   8'h1B ; 

   wire      ps2_rddata_valid;
   wire [7:0] ps2_rd_data; 
   wire      ps2_rx_ready;   
   wire     ps2_clk_in, ps2_data_in; 
   wire     ps2_clk_in_clean, ps2_data_in_clean; 

   assign   ps2_clk_in   = ps2_clk ; 
   assign   ps2_data_in  = ps2_data; 

`ifdef SIM
   assign ps2_clk_in_clean = ps2_clk_in ; 
   assign ps2_data_in_clean = ps2_data_in ; 
`else
   io_filter  #(.PIN_NUM (2 ) ) io_filter_inst (
         .clk     (  clk   ),
         .pin_in  ( { ps2_clk_in,      ps2_data_in} ),
         .pin_out ( { ps2_clk_in_clean,ps2_data_in_clean } ) 
   );
`endif

   ps2_host_rx ps2_host_rx_inst (
      .clk          ( clk           ),
      .rst          ( rst           ),
      .ps2_clk_in   ( ps2_clk_in_clean    ),
      .ps2_data_in  ( ps2_data_in_clean   ),
      .ps2_rx_en    ( ps2_rx_en     ),
      .ps2_rddata_valid ( ps2_rddata_valid ),
      .ps2_rd_data  ( ps2_rd_data   ), 
      .ps2_rx_ready ( ps2_rx_ready  )    
   );


   always @( posedge clk ) begin  
      key_up_tick    <= 1'b0;   
      key_down_tick  <= 1'b0; 
      if ( ps2_rddata_valid ) begin 
         case ( ps2_rd_data ) 
            KEY_W  :  key_up_tick   <= 1'b1 ; 
            KEY_S  :  key_down_tick <= 1'b1 ; 
         endcase 
      end  
   end



endmodule
